Solder masks used in encapsulation, assemblies including the solar mask, and methods

ABSTRACT

A carrier (e.g., a carrier substrate, such as a circuit board, etc.) may be modified to include a solder mask on a surface thereof. The solder mask, which may extend to or beyond an edge of the carrier, includes an opening that exposes at least one contact area of the carrier. The opening of the solder mask is configured and positioned such that a conductive element (e.g., a bond wire), at least a portion of which extends laterally, that may protrude from the contact area will be at least partially laterally surrounded by the solder mask. A retention element may be secured to the solder mask, over the conductive element and a portion of the opening of the solder mask, with a portion of the opening remaining exposed beyond the retention element to facilitate the introduction of encapsulant material into the opening and around the conductive element. Assemblies that include these features and assembly methods are also disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 11/108,151,filed Apr. 8, 2005, which is a continuation of application Ser. No.10/201,208, filed Jul. 22, 2002, now U.S. Pat. No. 6,984,545, issuedJan. 10, 2006.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to solder masks and use thereofin packaging semiconductor devices and, more specifically, to a methodfor encapsulating portions of a semiconductor device package using asolder mask as a mold for the encapsulant material.

2. Background of Related Art

As the dimensions of electronic devices are ever decreasing, the sizesof the structures used to package the microprocessors, memory devices,other semiconductor devices, and other electronic componentry must alsobecome more compact.

One approach to reducing the size of semiconductor device assemblies isto minimize the profiles of the semiconductor devices, as well as theconnectors and the electronic components to which the semiconductordevices are electrically connected, as well as to minimize the overallprofiles of such assemblies. One type of packaging technology that hasbeen developed to save space in this manner is the so-called “chip-scalepackage” (CSP).

An example of a CSP designed to save space is a board-over-chip (BOC)package. A typical BOC package comprises a carrier substrate that isconfigured to be secured over the active surface of a semiconductor die,wherein bond pads of the semiconductor die are exposed through anopening formed through the carrier substrate. The bond pads on thesemiconductor die are connected to conductive elements on the carriersubstrate using a step where wire bonds are formed and electricallyconnect the bonds pads to the conductive elements.

Following wire bonding, it is desirable to encapsulate the wire bondsbetween the semiconductor die and the carrier substrate. Encapsulationserves a variety of functions, including sealing the encapsulatedsurfaces from moisture and contamination and protecting the wire bondsand other components from corrosion and mechanical shock.

Encapsulants may be deposited from the top of the carrier substrate toencapsulate the semiconductor die and wire bonds. The material used forthe encapsulant typically comprises a flowable, dielectric material.Alternatively, a glob-top or other encapsulant may be formed over thewire bonds for protection. Glob-top structures use a high viscosityencapsulant, typically a silicone or an epoxy, such that theencapsulating material may be applied to a substantially planar surfacewithout being laterally confined. However, the height of the resultingglob-top structure may be higher than is required to properlyencapsulate the wire bonds and may interfere with subsequent packagingsteps.

After encapsulation, a solder stencil or solder mask may be placed orformed on the surface of the carrier substrate. Solder stencils andsolder masks typically include a number of openings in which solderballs may be placed or formed.

Conventional solder paste stencils and solder ball placement stencilsare substantially planar metal structures that are aligned with andsecured to a bond pad-bearing surface of a semiconductor device or aterminal-bearing surface of a carrier substrate, such as a printedcircuit board, on which solder balls are to be formed. Apertures thathave been formed through the stencil are aligned with corresponding bondpads or terminals. Such conventional solder stencils are designed toresist the adherence of solder and, thus, of the formed solder ballsthereto. Once such a solder stencil has been secured to a semiconductordevice or a carrier substrate, solder may be introduced onto the solderstencil, for example, by at least partially immersing the component oran assembly that includes the component in a solder bath to form solderballs on bond pads or terminals that are exposed through apertures ofthe solder stencil. When solder balls have been formed, a conventionalmetal solder stencil is typically removed from the component from whichthe solder balls protrude, then cleaned, and reused.

State-of-the-art solder masks are typically single-use structures thatare formed directly on the component on which solder balls are to beformed. These single-use solder masks may be formed from aphotoimageable material that, when cured, will withstand the conditionsto which such solder masks will be exposed, such as the typically hightemperatures of molten solder. Solder balls may be formed by employingthe same types of techniques, as described above, that are used withconventional, metal solder masks. Once the solder balls are formed, ifthe single-use solder mask was formed from a dielectric material and thesolder balls protrude a sufficient distance therefrom, the single-usesolder mask may remain in place on the component. Alternatively, thesolder mask may be removed from the component, such as by use ofsuitable photoresist stripping agents, to further expose the solderballs.

The solder mask prevents bridging of the solder material and shortingbetween the solder balls in the completed package. The presence of aglob-top structure may, however, make it difficult to place the soldermask over the carrier substrate, particularly if the glob-top materialhas moved too far laterally.

Accordingly, there is a need for a solder mask that may be positioned ona carrier substrate of a semiconductor device assembly prior toencapsulation of bond wires and which may remain in place as wirebonding operations are being conducted, as well as for assemblies andpackages including such solder masks and methods for forming and usingsuch solder masks.

SUMMARY OF THE INVENTION

The present invention relates generally to solder masks and use thereofin packaging semiconductor devices and, more specifically, to a methodfor encapsulating components of a package using a solder mask as a moldfor the encapsulant material.

An exemplary assembly or packaging method of the present inventionincludes providing a carrier substrate (e.g., a flexible, tape-typeinterposer, a rigid interposer, leads, etc.) with a slot formedtherethrough, and forming or placing a solder mask on a contactarea-bearing first surface of the carrier substrate. The solder maskincludes an opening through which the slot and first contact areas ofthe carrier substrate are exposed, as well as an array of smalleropenings that align with and expose corresponding second contact areasof the carrier substrate. A semiconductor die may be secured to anopposite, second surface of the carrier substrate and bond pads of thesemiconductor die may be electrically connected to corresponding contactareas on the first surface of the carrier substrate by positioning orforming intermediate conductive elements (e.g., bond wires, bondedleads, conductive tape-automated bonding (TAB) elements carried by aflexible dielectric film, etc.) therebetween. The intermediateconductive elements are then completely covered with an encapsulantmaterial, which is laterally confined within the central opening of thesolder mask. As the solder mask laterally confines the encapsulantmaterial, relatively low viscosity encapsulant materials may be used,resulting in an encapsulant structure which does not protrudesignificantly above the exposed surface of the solder mask.Subsequently, conductive structures, such as solder balls, may be formedon contact areas of the carrier substrate that are exposed throughapertures of the solder mask.

A semiconductor device assembly or package incorporating teachings ofthe present invention includes a substantially planar carrier substratewith a solder mask formed or positioned on a first surface thereof. Asemiconductor die may be secured to an opposite, second surface of thecarrier substrate, with at least one intermediate conductive elementelectrically connecting a bond pad of the semiconductor die and acorresponding first contact area of the carrier substrate. The assemblyor package may also include a quantity of encapsulant material, which islaterally confined by the solder mask and encapsulates the at least oneintermediate conductive element. Additionally, the assembly or packagemay include at least one conductive structure, such as a solder ball,secured to a corresponding second contact area of the carrier substrateand protruding from the exposed surface of the solder mask.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The nature of the present invention, as well as exemplary embodimentsand other features and advantages of the present invention, may be moreclearly understood by reference to the following detailed description ofthe invention, to the appended claims, and to the several drawingsherein, wherein:

FIGS. 1A and 1B are cross-sectional views of assemblies including thesolder mask of the present invention;

FIG. 2 is a perspective view of the assembly depicted in FIG. 1B;

FIG. 3 is an inverted perspective view of the assembly depicted in FIGS.1B and 2; and

FIG. 4 is a perspective view of the assembly of FIGS. 1B-3 where anencapsulant has been added.

DETAILED DESCRIPTION OF THE INVENTION

Generally, the present invention includes methods of encapsulatingintermediate conductive elements, such as bond wires, and semiconductordice in assemblies and relatively thin-profile packages in which acarrier substrate is secured to the active surface of a semiconductordie, such as BOC-type assemblies and packages, including, withoutlimitation, BGA configurations, tape BGA (TBGA) configurations, andmicro tape BGA (MTBGA) configurations of such assemblies and packages.While the present invention is described in terms of certain specific,exemplary embodiments, the specific details of these embodiments are setforth in order to provide a thorough understanding of the presentinvention. It will be apparent, however, that the present invention maybe practiced in various combinations of the specific exemplaryembodiments presented herein.

It will be appreciated that the drawings described herein are not drawnto scale, but are for exemplary purposes only. Referring now to drawingFIG. 1A, there is shown a cross-sectional view of an assembly generallyat 10 that includes a solder mask 12 according to the present inventionand a carrier substrate 15 upon which the solder mask 12 is carried. Inthe illustrated embodiment, the carrier substrate 15 is an interposerwith opposite major upper and lower surfaces 16 and 18, respectively. Aslot 17 or other opening is formed through the carrier substrate 15,somewhat centrally in the depicted embodiment, and extends from uppersurface 16 to lower surface 18. As known to those of ordinary skill inthe art, the carrier substrate 15 may be formed to a desired shape andthickness and with required features for use in forming a functionalsemiconductor package.

The material used to fabricate the carrier substrate 15 may comprise arelatively thin, flexible film of an electrically insulative material,such as an organic polymer resin (e.g., polyimide). If the carriersubstrate 15 comprises an MTBGA substrate, the thickness thereof may beon the order of about 50 μm to about 75 μm. Alternatively, the carriersubstrate 15 may comprise a somewhat rigid, substantially planar member,which may be fabricated from any known, suitable materials, including,but not limited to, insulator-coated silicon, a glass, a ceramic, anepoxy resin (e.g., FR-4, FR-5, etc.), bismaleimide-triazine (BT) resin,or any other material known in the art to be suitable for use as acarrier substrate. A BT resin substrate may have a thickness of about125 μm. Although the illustrated embodiment depicts the carriersubstrate 15 as being an interposer, a solder mask 12 incorporatingteachings of the present invention may also be used with other types ofcarrier substrates, such as circuit boards, leads, and the like, withoutdeparting from the scope of the present invention.

As shown, the upper surface 16 of the carrier substrate 15 carriesconductive traces 19, first contact areas 21 located proximate the slot17, and second contact areas 22 located peripherally relative to thefirst contact areas 21. As shown, the second contact areas 22 arearranged in an area array, although other arrangements of second contactareas 22 are also within the scope of the present invention. It will beappreciated that the conductive traces 19, first contact areas 21, andsecond contact areas 22 may comprise, without limitation, conductivelydoped polysilicon, a conductive metal or metal alloy, conductive orconductor-filled elastomer, or any other conductive material used forelectrical connections known to those of ordinary skill in the art.

The solder mask 12 is formed as a substantially planar member with arelatively large central opening 13 formed therethrough. In addition,the solder mask 12 includes smaller apertures 14 that are positioned soas to expose corresponding second contact areas 22 of the carriersubstrate 15 and to facilitate the formation of solder balls or otherdiscrete conductive elements 52 (FIG. 1B) on the second contact areas22. As illustrated in FIG. 1A, the solder mask 12, as configured, issuperimposed over a substantial portion of the carrier substrate 15(also shown in FIG. 2). The solder mask 12 has an upper surface 20 and alower surface 23 (as oriented in FIGS. 1A and 1B). In the illustratedembodiment, the lower surface 23 of the solder mask 12 is secured to theupper surface 16 of the carrier substrate 15. As known in the art, anadhesive material may be used to attach the solder mask 12 to the uppersurface 16 of the carrier substrate 15. Alternatively, the material ofthe solder mask 12 may secure the solder mask 12 to the upper surface 16of the carrier substrate 15.

The solder mask 12 may be prefabricated and adhered to the carriersubstrate 15 or it may be formed on the carrier substrate 15, bothprocesses that are known in the art. The material used for the soldermask 12 is an electrically insulative material and, if it is to remainon a functioning semiconductor die 24 (FIG. 1B), the material of thesolder mask 12 may be selected to have a coefficient of thermalexpansion (CTE) similar to that of the material used for the carriersubstrate 15. When the carrier substrate 15 and solder mask 12 havesimilar or substantially “matched” CTEs, the likelihood that theseelements of a package will be mechanically stressed or that the soldermask 12 will delaminate from the carrier substrate during thermalcycling of a semiconductor die 24 (FIG. 1B), which may occur duringtesting or operation thereof, is reduced. Materials that may be used forthe solder mask 12 include, but are not limited to, plastics, resins,acrylics, urethanes, and polyimides.

As an example of fabrication of the solder mask, known photolithographyprocesses may be employed. When photolithography processes are used, alayer of dielectric photoimageable material, such as a photoresist, maybe formed on the upper surface 16 of the carrier substrate 15 by knownprocesses, such as by spin-on techniques. The photoimageable materialmay then be selectively exposed or patterned, then developed, followedby removal of unpolymerized portions thereof to form the solder mask 12therefrom.

Another exemplary method for forming a solder mask includes screenprinting a layer of dielectric material, such as a polyimide, ontoselected regions of the upper surface 16 of the carrier substrate 15.

In yet another exemplary method, a solder mask 12 may be formed aseither a single layer or a plurality of contiguous, at least partiallysuperimposed, mutually adhered layers of dielectric material by knownstereolithography techniques. In such techniques, selected regions of alayer of at least partially unconsolidated material, such as an uncuredphotoimageable polymer, are selectively consolidated, such as byexposing the uncured photoimageable polymer in the selected regions toan energy beam comprising a curing wavelength of radiation. This processmay be repeated until a structure of the desired height is formed.

Referring now to FIG. 1B, there is shown a cross section of the assembly10 of FIG. 1A that also includes a semiconductor die 24. Thesemiconductor die 24 has an active surface 26 and an opposite back side28. As known to those of ordinary skill in the art, bond pads 30 arelocated on the active surface 26 of the semiconductor die 24. The bondpads 30 facilitate the communication of electrical signals to and fromvarious circuit elements, or “integrated circuits” (not shown), that maybe present on or within the active surface 26 of the semiconductor die24. As illustrated, the semiconductor die 24 is attached to the carriersubstrate 15 with an adhesive element 32, as known in the art. Theadhesive element 32 may comprise a film or tape which is at leastpartially coated with adhesive material or a quantity of adhesivematerial, such as a pressure sensitive adhesive or a curable adhesive(e.g., an epoxy). If the adhesive element 32 comprises a polymeric filmor tape, the adhesive element may also include an opening 38therethrough that corresponds to and aligns with the slot 17 in thecarrier substrate 15.

Alternatively, the adhesive element 32 may comprise a plurality ofindividual strips. If the adhesive element 32 comprises strips, anyremaining spaces between superimposed portions of the semiconductor die24 and the carrier substrate 15 may be filled with an underfill materialof a type known in the art (e.g., a low viscosity silicone, epoxy,etc.).

Although FIG. 1B depicts the bond pads 30 (shown also in FIG. 2) alignedsubstantially linearly along the center of the active surface 26 of thesemiconductor die 24, it will be appreciated that other bond pad 30arrangements are meant to be encompassed by the present invention. Asdepicted in FIG. 1B, after the semiconductor die 24, the adhesiveelement 32, and the carrier substrate 15 have been properly positionedrelative to one another and secured together to form the assembly 10,each bond pad 30 of the semiconductor die 24 may be electricallyconnected to its corresponding first contact area 21 on the carriersubstrate 15. As depicted in FIG. 1B, each such electrical connectionmay be accomplished with an intermediate conductive element 40, such asa bond wire, a conductive TAB element carried upon a flexible dielectricfilm, a bonded lead, or the like, which extends between each bond pad 30and its corresponding first contact area 21, as well as through the slot17 of the carrier substrate 15.

Referring now to FIG. 2, there is shown a perspective view of theassembly 10 shown in FIG. 1B. As illustrated, the solder mask 12overlies the periphery of the carrier substrate 15. The central opening13 in the solder mask 12 exposes the intermediate conductive elements40, a portion of the upper surface 16 of the carrier substrate 15, thefirst contact areas 21 of the carrier substrate 15, and a portion of theactive surface 26 of the semiconductor die 24 along which the bond pads30 are located.

To seal the components from moisture, contamination and corrosion, andto protect against mechanical shock, the components exposed through thecentral opening 13 in the solder mask 12 are encapsulated. As known tothose of ordinary skill in the art, an encapsulant material 46 (as shownin FIG. 4) may be applied from a top side 34 of an assembly 10 of thepresent invention or from a bottom side 36 of an inverted assembly 10′that incorporates teachings of the present invention, as depicted inFIG. 3. To apply the encapsulant material 46 from the bottom side 36 ofthe inverted assembly 10′, any openings therein from which theencapsulant material 46 may escape may be covered with a coverlet 47.

A suitable, known type of dielectric encapsulant material 46 may beintroduced into the central opening 13 of the solder mask 12, as well asinto the slot 17 of the carrier substrate 15 and around the intermediateconductive elements 40 that are laterally contained within the centralopening 13 and slot 17. As shown in FIG. 2, the slot 17 does not extendbeyond an outer periphery of the semiconductor die 24. Thus, thesemiconductor die 24, the edges of opening 38 of the adhesive element 32and of the slot 17 of the carrier substrate 15, and the solder mask 12together contain the encapsulant material 46. In the illustratedembodiment, the encapsulant material 46 is introduced using anencapsulant dispenser needle 48 (as shown in FIG. 3). However, theencapsulant material 46 may be introduced using any suitable processknown in the art. The solder mask 12 functions to laterally confine theencapsulant material 46. The encapsulant material 46 is introduced untilan upper surface of the encapsulant material 46 is substantially levelwith the upper surface 20 of the solder mask 12 if encapsulant material46 is introduced while an assembly 10 is oriented as shown in FIGS. 1Band 2.

The encapsulant material 46 may comprise a flowable, dielectric materialwith a CTE substantially the same as the CTEs of the materials fromwhich the carrier substrate 15 and the solder mask 12 are formed. Itwill be appreciated that the encapsulant material 46 may comprise, butis not limited to, a thermoplastic resin, an epoxy, a polyester, apolyimide, a cyanoacrylate, a silicone, and a urethane. Depending on thetype of encapsulant material 46, curing or setting thereof (e.g., byapplication of heat and/or pressure, by exposure of photoimageablepolymer encapsulant materials to an appropriate wavelength of radiation,by use of an appropriate catalyst, or in any other manner known to thoseof ordinary skill in the art) may be necessary.

Referring now to FIG. 3, there is shown an inverted perspective view ofa semiconductor device assembly 10′ that includes a slot 17′ and anopening 38′ in the carrier substrate 15′ and the adhesive element 32′,respectively, that extend beyond at least one outer peripheral edge ofthe semiconductor die 24, leaving a space 44 uncovered by thesemiconductor die 24. A coverlet 47, such as a film, tape, or othersubstantially planar member, is secured to the upper surface 20 (nowinverted) of the solder mask 12. The coverlet 47 may be at leastpartially coated with an adhesive material 50 to secure the same to theupper surface 20 of the solder mask 12. The adhesive material 50 used onthe coverlet 47 facilitates the ready removal of the coverlet 47 fromthe upper surface 20 of the solder mask 12. The coverlet 47 may alsohave sufficient flexibility to conform to any irregularities ornonplanarities of the upper surface 20 of the solder mask 12.

An encapsulant material 46 (FIG. 4) may be introduced into the bottomside 36 of the assembly 10′ through the space 44, which is continuouswith the slot 17′ of the carrier substrate 15′ and the central opening13 of the solder mask 12, by way of an encapsulant dispenser needle 48or otherwise, as known in the art. The coverlet 47 precludes loss ofencapsulant material 46 during inversion of assembly 10′. Air may bedisplaced by encapsulant material 46 through the open space 44 at theend of the slot 17′, opposite that into which the encapsulant material46 is introduced.

Referring now to FIG. 4, there is shown the assembly 10 of FIG. 2 afterthe encapsulant 46 material has cured or set. As previously described,it is apparent that an upper surface 51 of the solidified encapsulantmaterial 46 is substantially coplanar with the upper surface 20 of thesolder mask 12. Referring again to FIG. 1B, it will be apparent that theencapsulant 46 material substantially encapsulates the intermediateconductive elements 40, the first contact areas 21, and the bond pads 30and adjacent regions of the active surface 26 of the semiconductor die24. The top of each intermediate conductive element 40 and the uppersurface 51 of the encapsulant material 46 are separated by a distancewhich is sufficient to prevent electrical interference between signalspassing through intermediate conductive elements 40 and conductiveelements or components that are positioned adjacent to the upper surface51 (FIG. 1B) of the encapsulant material 46. The distance between thetop of each intermediate conductive element 40 and the upper surface 51of the encapsulant material 46 may, for example, be as much as 25 μm orgreater.

Solder balls or other discrete conductive elements 52 (FIG. 1B) may thenbe formed by known processes, such as by immersing assembly 10 in asolder bath.

It will be appreciated that the thickness of the solder mask 12 from theupper surface 20 to the lower surface 23 may be varied depending on theheight of the intermediate conductive elements 40. It may be desirableto have a layer of encapsulant material 46 that is approximately 25 μmbetween the upper surface of the intermediate conductive elements 40 andthe upper surface 20 of the solder mask 12. Therefore, the solder mask12 is designed such that once the encapsulant material 46 has beendispensed, the upper surface 51 of the encapsulant material 46 and theupper surface 20 of the solder mask 12 is approximately 25 μm above theintermediate conductive elements 40. It may also be desirable to designthe solder mask 12 to be about half as thick as solder balls (not shown)to accommodate a subsequent solder ball formation process. Typically,the solder mask 12 of the present invention will be between about 50 μmand about 100 μm thick, as opposed to 25-50 μm thick for conventionalsolder masks.

Once the encapsulant material 46 has cured or set and solder balls orother discrete conductive elements 52 (FIG. 1B) have been formed in theapertures 14 of the solder mask 12 and on the second contact areas 22 ofthe carrier substrate 15, it will be appreciated that the solder mask 12may be left in place during subsequent use (e.g., packaging of theassembly 10 or assembly thereof with other semiconductor devicecomponents, such as circuit boards, or other electronic components), orthe solder mask 12 may be removed from the assembly 10. When left inplace, the solder mask 12 may act as a spacer between the carriersubstrate 15 and a higher-level package component or another electronicdevice (not shown).

Although the present invention has been shown and described with respectto illustrated embodiments, various additions, deletions andmodifications that are obvious to a person of ordinary skill in the artto which the invention pertains, even if not shown or specificallydescribed herein, are deemed to lie within the scope of the invention asencompassed by the following claims.

1. A method for preparing a semiconductor device assembly for at leastpartial packaging, comprising: disposing a solder mask over a carrier,at least partially laterally around an extent of at least one at leastpartially laterally extending intermediate conductive element thatprotrudes beyond a plane within which a surface of the carrier islocated; and securing a retention element to the solder mask, over theat least one at least partially laterally extending intermediateconductive element, with an opening remaining so that encapsulantmaterial may be introduced at least partially onto the at least one atleast partially laterally extending intermediate conductive element. 2.The method of claim 1, wherein disposing comprises disposing the soldermask such that the at least one at least partially laterally extendingintermediate conductive element is located within at least one at leastpartially laterally confined opening through the solder mask.
 3. Themethod of claim 1, further comprising: securing at least onesemiconductor device to the carrier and electrically connecting at leastone bond pad of the at least one semiconductor device and acorresponding contact of the carrier with the at least one at leastpartially laterally extending intermediate conductive element.
 4. Themethod of claim 3, wherein electrically connecting comprises disposingthe at least one at least partially extending intermediate conductiveelement through a plane that extends through the carrier.
 5. The methodof claim 1, wherein disposing comprises positioning a preformed soldermask on a surface of the carrier.
 6. The method of claim 5, whereindisposing further includes securing the preformed solder mask to thesurface.
 7. The method of claim 1, wherein disposing comprises formingthe solder mask on a surface of the carrier.
 8. The method of claim 7,wherein forming comprises forming the solder mask from a photoimageablematerial.
 9. The method of claim 8, wherein forming comprises formingthe solder mask from a photoresist.
 10. The method of claim 7, whereinforming comprises forming the solder mask by consolidatingunconsolidated material in accordance with a program.
 11. The method ofclaim 1, wherein disposing comprises disposing a solder mask having athickness that exceeds a height the at least one at least partiallylaterally extending intermediate conductive element protrudes beyond theplane within which the surface of the carrier is located.
 12. The methodof claim 1, further comprising: positioning at least one aperture of thesolder mask over at least one contact of the carrier.
 13. The method ofclaim 12, further comprising: disposing conductive material within theat least one aperture.
 14. A method for protecting intermediateconductive elements of a semiconductor device assembly, comprising:disposing a solder mask over a carrier, at least partially laterallyaround an extent of at least one at least partially laterally extendingintermediate conductive element that protrudes beyond a plane withinwhich a surface of the carrier is located; securing a retention elementto the solder mask, over the at least one at least partially laterallyextending intermediate conductive element, with at least one opening inflow communication with the at least one at least laterally extendingintermediate conductive element remaining; and introducing encapsulantinto the at least one opening, beneath the retention element, and intoonto at least a portion of the at least one at least laterally extendingintermediate conductive element.
 15. The method of claim 14, furthercomprising: removing the retention element following the act ofintroducing.
 16. The method of claim 14, further comprising: removingthe solder mask following the act of introducing.
 17. The method ofclaim 14, wherein disposing comprises disposing the solder mask suchthat the at least one at least partially laterally extendingintermediate conductive element is located within at least one at leastpartially laterally confined opening through the solder mask.
 18. Themethod of claim 14 further comprising: securing at least onesemiconductor device to the carrier and electrically connecting at leastone bond pad of the at least one semiconductor device and acorresponding contact of the carrier with the at least one at leastpartially laterally extending intermediate conductive element.
 19. Themethod of claim 18, wherein electrically connecting comprises disposingthe at least one at least partially extending intermediate conductiveelement through a plane that extends through the carrier.
 20. The methodof claim 14, wherein disposing comprises positioning a preformed soldermask on a surface of the carrier.
 21. The method of claim 20, whereindisposing further includes securing the preformed solder mask to thesurface.
 22. The method of claim 14, wherein disposing comprises formingthe solder mask on a surface of the carrier.
 23. The method of claim 22,wherein forming comprises forming the solder mask from a photoimageablematerial.
 24. The method of claim 23, wherein forming comprises formingthe solder mask from a photoresist.
 25. The method of claim 22, whereinforming comprises forming the solder mask by consolidatingunconsolidated material in accordance with a program.
 26. The method ofclaim 14, wherein disposing comprises disposing a solder mask having athickness that exceeds a height the at least one at least partiallylaterally extending intermediate conductive element protrudes beyond theplane within which the surface of the carrier is located.
 27. The methodof claim 14, further comprising: positioning at least one aperture ofthe solder mask over at least one contact of the carrier.
 28. The methodof claim 27, further comprising: disposing conductive material withinthe at least one aperture.
 29. A method for modifying a carrier,comprising: providing a carrier including at least one contact area on asurface thereof; and disposing a solder mask including an opening on thesurface of the carrier, with an edge of the solder mask extending to anedge of the carrier and the at least one contact area of the carrierexposed through the opening.
 30. The method of claim 29, whereindisposing includes positioning a preformed solder mask on the surface ofthe carrier.
 31. The method of claim 30, wherein disposing furtherincludes securing the preformed solder mask to the surface of thecarrier.
 32. The method of claim 29, wherein disposing comprises formingthe solder mask on the surface of the carrier.
 33. The method of claim32, wherein forming comprises forming the solder mask from aphotoimageable material.
 34. The method of claim 33, wherein formingcomprises forming the solder mask from a photoresist.
 35. The method ofclaim 32, wherein forming comprises forming the solder mask byconsolidating unconsolidated material in accordance with a program. 36.The method of claim 29, wherein disposing comprises locating at leastone aperture of the solder mask at least partially over a contactexposed at the surface of the carrier.
 37. A semiconductor deviceassembly, comprising: a carrier including a substantially planarstructure and at least one first contact exposed at a first surface ofthe substantially planar structure; and a solder mask positioned on thefirst surface, extending to an outer peripheral edge of the firstsurface, and comprising at least one opening for laterally surroundingat least a portion of at least one intermediate conductive element, atleast a portion of which extends laterally, protruding beyond a plane inwhich the first surface of the carrier is located, the at least onefirst contact area of the carrier being exposed through the at least oneopening.
 38. The semiconductor device assembly of claim 37, wherein atleast one opening is formed through the substantially planar structureof the carrier.
 39. The semiconductor device assembly of claim 38,wherein the first contact is exposed at a location proximate to the atleast one opening of the carrier.
 40. The semiconductor device assemblyof claim 39, wherein the at least one opening of the carrier is at leastpartially exposed through the at least one opening of the solder mask.41. The semiconductor device assembly of claim 40, further comprising:at least one semiconductor device secured to a second surface of thecarrier opposite the first surface thereof, at least one bond pad of theat least one semiconductor device exposed through said the at least oneopening of the solder mask and the at least one opening of the carrier.42. The semiconductor device assembly of claim 41, further comprising:at least one intermediate conductive element extending between the atleast one bond pad and the at least one first contact area.
 43. Thesemiconductor device assembly of claim 42, wherein a thickness of thesolder mask exceeds a distance the at least one intermediate conductiveelement protrudes beyond the plane in which the first surface of thecarrier is located.
 44. The semiconductor device assembly of claim 42,further comprising: encapsulant material within the at least one openingof the substantially planar structure of the carrier and the at leastone opening of the solder mask.
 45. The semiconductor device assembly ofclaim 44, wherein a surface of the encapsulant material is substantiallylevel with an outer surface of the solder mask.
 46. The semiconductordevice assembly of claim 37, wherein the carrier includes at least onesecond contact area on the first surface thereof.
 47. The semiconductordevice assembly of claim 46, wherein the at least one second contactarea is at least partially exposed through an aperture of the soldermask.
 48. The semiconductor device assembly of claim 47, furthercomprising: at least one discrete conductive element protruding from theat least one second contact and extending beyond a surface of the soldermask.
 49. The semiconductor device assembly of claim 37, wherein thesolder mask comprises a material with a coefficient of thermal expansionsubstantially the same as a material of the carrier.
 50. Thesemiconductor device assembly of claim 37, wherein the solder maskcomprises an insulative material.
 51. The semiconductor device assemblyof claim 37, wherein the solder mask comprises a cured photoimageablematerial.
 52. The semiconductor device assembly of claim 37, wherein thesolder mask includes a plurality of adjacent, mutually adhered regions.53. The semiconductor device assembly of claim 37, further comprising: aretaining element over a portion of the opening of the solder mask.